Power consumption of recent semiconductor integrated circuits tends to be increased due to their high functionalities. For instance, recent display panel drivers suffer from a significant increase in power consumption due to an increase in the number of pixels of display panels. Power consumption reduction is one of the most significant issues of recent integrated circuits.
The through current of the inverter circuit, particularly the CMOS (complementary metal oxide semiconductor) inverter, is known as one cause of the increase in the power consumption of a semiconductor integrated circuit. Discussed below is the through current of a CMOS inverter.
FIG. 1 illustrates the configuration of a typical CMOS inverter, which is denoted by numeral 100. The CMOS inverter 100 includes a PMOS transistor MP1 and an NMOS transistor MN1. The gates of the PMOS transistor MP1 and the NMOS transistor MN1 are commonly connected to an input terminal 101 to which an input signal VIN1 is supplied. The drains of the PMOS transistor MP1 and the NMOS transistor MN1 are commonly connected to an output terminal 102 from which an output signal VOUT1 is externally output. The source of the PMOS transistor MP1 is connected to a positive-side terminal 103 (for example, a power supply terminal) and the source of the NMOS transistor MN1 is connected to a negative-side terminal 104 (for example, a circuit-ground terminal). In FIG. 1, the legend “CLOAD” denotes a load capacitance connected to the output terminal 102 of the CMOS inverter 100.
FIG. 2 is a timing chart illustrating one example of the operation of the CMOS inverter 100 illustrated in FIG. 1. Illustrated in FIG. 2 are the voltage levels of the input signal VIN1 and the output signal VOUT1, and the current levels |Ip1|, |In1| of the currents Ip1, In1 flowing through the PMOS transistor MP1 and the NMOS transistor MN1. It is assumed that the input signal VIN1 is initially set to the low level (the circuit-ground level VSS in the operation illustrated in FIG. 2). In this situation, the PMOS transistor MP1 is placed in the on-state and the NMOS transistor MN1 is placed in the off-state, whereas the output signal VOUT1 is set to the high level (the power supply level VDD, in the operation illustrated in FIG. 2).
When the input signal VIN1 is switched from the low level to the high level, the output signal VOUT1 is switched from the high level to the low level, since the PMOS transistor MP1 is turned off and the NMOS transistor MN1 is turned on. In detail, the turn-on of the NMOS transistor MN1 generates a current flow from the load capacitance CLOAD to the negative-side terminal 104 through the NMOS transistor MN1, discharging the charges from the load capacitance CLOAD. This allows pulling down the output signal VOUT1 to the low level. It should be noted that, in FIG. 2, time t1 denotes the time when the switching of the input signal VIN1 from the low level to the high level is started and time t2 denotes the time when the output signal VOUT1 is set to the low level. The output signal VOUT1 is set to the low level at time t2, which is the time when the falling time tF1 has elapsed since time t1.
Between time t1 and time t2, there is a period during which both of the PMOS transistor MP1 and the NMOS transistor MN1 are turned on, and this causes a current flow through both of the PMOS transistor MP1 and the NMOS transistor MN1 during this period. In other words, a through current undesirably flows during the period between time t1 and time t2, during which the output signal VOUT1 is being switched from the high level to the low level.
The same applies to the case when the input signal VIN1 is switched from the high level to the low level. After the switching of the input signal VIN1 from the high level to the low level is started at time t3, the output signal VOUT1 is pulled up to the high level at time t4, which is the time when the rising time tR1 has elapsed since time t3. Between the time t3 and the time t4, there is a period during which both of the PMOS transistor MP1 and the NMOS transistor MN1 are turned on and this causes a current flow through both of the PMOS transistor MP1 and the NMOS transistor MN1 during this period. In other words, a through current undesirably flows during the period between time t3 and time t4, during which the output signal VOUT1 is being switched from the low level to the high level.
Various techniques have been proposed to reduce the through current. For instance, Japanese Patent Application Publications No. 2005-175540 A and 2010-178038 A disclose a technique for reducing the through current by controlling the timing of the turn-on-and-off of the NMOS and PMOS transistors of a CMOS inverter by using delay elements (or delay circuits). Japanese Patent Application Publication No. 2011-87036 A discloses an output buffer circuit including a detection circuit configured to detect the voltage on the common node from which the output signal is output and control the turn-on-and-off of the transistors of the CMOS inverter in response to the detected voltage.
However, there is room for improvement in these known techniques for reduction of the current reduction.